1. Field of the Invention
The present invention relates to a power semiconductor device.
2. Description of the Related Art
One of conventional power semiconductor devices is shown in FIG. 13.
Disposed on the metallic base board (2) is an insulating substrate (4) of ceramics having metal-plated circuit patterns on both sides, and mounted on the insulating substrate (4) are a switching power semiconductor element (6) such as IGBT, MOSFET or the like and a free wheeling diode (8). The switching power semiconductor element (6) and the free wheeling diode (8) are connected to a casing (18) having external terminals built therein (an insert casing), through the external terminals. The switching power semiconductor element (6) such as IGBT is so disposed that the upper side (surface) thereof serves as an emitter face and the lower side (reverse) thereof, as a collector face. The free wheeling diode (8) is so disposed that the upper side (surface) thereof serves as an anode face, and the lower side (reverse) thereof, as a cathode face. The circuit as a whole comprises a pattern formed on the insulating substrate (4) and wires (20), and is connected to the casing (18). Gel (or a resin, or gel and a resin) (36) is inserted into the casing (18) so as to protect the element and the circuit, and the casing (18) is covered with a lid.
In this power semiconductor device, the connection of the emitter face of the switching power semiconductor element (6) is made through the wires (20), and this connection method arises the following problems.
Firstly, there is a limit in the capacity of a current since the wire (20) is thin. In practical use, a required capacity of current is ensured for a main circuit by using thicker wires, or increasing the number of wires (20). However, this method requires spaces for wire bonding, and therefore has a limit in miniaturization of the elements and the device. Secondly, the circuit resistance becomes larger because of the use of the thin wires (20). While this problem also can be solved by using thicker wires or increasing the number of the wires (20), there are limits as mentioned above. Thirdly, heat is locally accumulated, since a current is concentrated on the joints of the wires on the switching power semiconductor element (6). While the concentration of heat is reduced by decentralizing the joints of the wires on the element, heat is not completely decentralized. Fourthly, the gate may oscillate when a short circuit occurs in the semiconductor device. In the power semiconductor device, a wire (20) is bonded to each of the emitter cells of the switching power semiconductor element (6), and the cells are connected to one another through the pattern formed on the insulating substrate (4) to which the wires (20) are bonded. Such connection causes unbalance between each of the cells, and thus, the gate oscillates when a short circuit occurs in the semiconductor device. As a result, the device may be destructed or may cause malfunction. It may be possible to solve this problem by direct stitch connection of each of the cells through the wires. However, the number of operations for wire bonding is increased, and the area of the device for such wire bonding is also increased. As a result, there still remain similar limits to the first problem. Fifthly, spaces for bonding the wires are needed.
The foregoing are main problems in relation to the wires (20). There are further problems in relation to heat radiation. In the conventional semiconductor device, heat radiation is carried out by applying grease to the reverse side of the base board and screwing heat radiation fins. In this case, only one side of the device is used for heat radiation.
JP-A-10-56131 discloses a technique in which connection of main electrodes is made through a plurality of bumps in a IGBT module having circuit patterns on the upper and lower sides thereof. JP-A-8-8395 discloses a technique in which an element analogous to the connective conductor is used. JP-A-10-233509 describes an example of a device having a plurality of bumps provided therein. JP-A-6-302734 discloses a technique in which two substrates are connected to each other through a spring. JP-A-8-17972 discloses a technique for embedding poles and metal balls in bumps for use in connection of a package mother board. JP-A-2002-16215 and JP-A-2002-76254 disclose IPMs each of which uses two lead frames, i.e. upper and lower lead frames.